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L9848
OCTAL CONFIGURABLE LOW/HIGH SIDE DRIVER
s s s s s
Configurable up to 6 high side drivers RDSON=max.1.5@Tj=25C Current limit of each output at min. 0.8A Supply voltage 4.75V to 5.25V Output voltage clamping min. 35V (low side mode) Output voltage clamping -30V (high side mode) SPI interface for data communication Additional PWM inputs for 2 outputs Thermal shutdown for all outputs Open load detection in off mode Reverse battery protection for outputs (amb) Ground disconnection for high side configured outputs be used as either internal low or high side drives in any combination (Outputs 1-6). In addition, 2 outputs are capable of being PWMed via an external pin (Outputs 5-6). The integrated standard serial peripheral interface (SPI) controls all outputs and provides diagnostic information. Integrated clamping circuits, waveshaping, protection against positive and negative voltage transients and thermal shutdown for all outputs open a wide range of automotive and industrial applications
SO28 ORDERING NUMBER: L9848
s s s s s s s
DESCRIPTION The L9848 IC is a highly flexible monolithic medium current output driver that incorporates 2 dedicated low side outputs (Outputs 7-8) and 6 outputs that can BLOCK DIAGRAM
VDD=5V
DRN1 SCLK SRC1
Gate Driver Interface
Di
DRN2 SRC2 DRN3 SRC3 DRN4 SRC4 DRN5 SRC5 DRN6 SRC6 DRN7
SPI
DO CS
PWM IN5 PWM IN6
1 1
DRN8
SO-28 Prepared by G. Bober, July 5, 2001 System Competence Center Automotive AutomotiveGND Business Unit Europe Page 9
July 2003
(R)
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L9848
PIN DESCRIPTION
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin GND VDD DRN8 SRC2 DRN2 SRC1 DRN1 NC IN6 SRC6 DRN6 NC NC SCLK DI CS NC DRN5 SRC5 IN5 NC DRN3 SRC3 DRN4 SRC4 DRN7 NC DO Analog ground 5V supply input Drain of low side driver #8 Source of configurable driver #2 Drain of configurable driver #2 Source of configurable driver #1 Drain of configurable driver #1 Not connected PWM input for driver #6 Source of configurable driver #6 Drain of configurable driver #6 Not connected Not connected SPI serial clock input SPI data in SPI chip select (active high) Not connected Source of configurable driver #5 Drain of configurable driver #5 PWM input for driver #5 Not connected Source of configurable driver #3 Drain of configurable driver #3 Source of configurable driver #4 Drain of configurable driver #4 Drain of low side driver #7 Not connected SPI data out Description
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L9848
ABSOLUTE MAXIMUM RATINGS For voltages and currents applied externally to the device. This part may be irreparably damaged if taken outside the specified absolute maximum rating range
Symbol VDD Pin voltages VCS, VDI, VDO, VSCLK VIN5, VIN6 VSRC1 - VSRC8 VDRN1 - VDRN6 VSRC1 - VSRC8 VDRN1 - VDRN6 Eout 1-8
(*) Internally limited
Parameter Supply voltage
Value -0.3 to 7.0
Unit V
Data lines voltages Input voltages Output DC voltages Output DC voltages Output transient voltages Output transient voltages Max. dissipation energy (@ 300mA)
-0.3 to 7.0 -0.3 to 7.0 -13.5 to 40 -13.5 to 60 (*) -20 to 40 -20 to 60 60
V V V V V V mJ
OPERATION CONDITIONS This part may not operate if taken outside the maximum ratings. Once the condition is returned to within the specified maximum rating or the power is re-cycled, the part will recover with no damage or degradation.
Symbol VDD VBatt Iout Tj Supply voltage Battery supply voltage Output current (channel 1-8) Junction temperature Parameter Value 4.75 to 5.25 9 to 18 350 -40 to 150 Unit V V mA C
THERMAL DATA
Symbol Tst Rth(j-a) Rth(j-a)
(1)
Parameter Storage temperature Thermal resistance junction-ambient Thermal resistance junction-ambient(1)
Value -65 to 150 max. 70 max. 50
Unit C C/W C/W
With 6cm2 on board heat sink area.
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L9848
ELECTRICAL CHARACTERISTCS DC Characteristics (Tj=-40C to 150C, VDD=4.75Vdc to 5.25Vdc, VBatt=9V to 18V, unless otherwise specified)
Symbol VIN5,6(ih) VIN5,6(il) IIN5,6(il) IIN5,6(ih) VCS(ih) VCS(il) ICS(il) ICS(ih) VSCLK(ih) VSCLK(il) ISCLK(il) ISCLK(ih) VDI(ih) VDI(il) IDI((il) IDI((ih) IVDD IVDD VDO(ol) VDO(oh) IDO(zol) IDO(zoh) IDRN1-8(lk) ISRC1-6(lk) Parameter IN5,6 Input Voltage 0.8 IN5,6 Input Current CS Input Voltage 0.8 CS Input Current SCLK Input Voltage 0.8 SCLK Input Current DI Input Voltage 0.8 DI Input Current VDD Current VDD Current DO Output Voltage DO Tri-State Current DRN1-8 Leakage Current (low side) SRC1-6 Leakage Current (high side) VDI = 0Vdc VDI = VDD All outputs ON All outputs OFF IDO=1.6mA IDO=-200A VDO = 0Vdc VDO = VDD VDD=0.5Vdc, VSRC1-6=0Vdc, VDRN1-8=18Vdc VDD=0.5Vdc, VSRC1-6=0Vdc, VDRN=35V VDD=0.5Vdc, VSRC1-6=0Vdc, VDRN1-8=18Vdc VDD=0.5Vdc, VSRC1-6=0Vdc, VDRN=35V VSRC1-6=0Vdc, DI=00h, VDRN1-8 = 18Vdc VSRC1-6=0Vdc, DI=00h, VDRN=35V -5 -10 50 50 -80 -100 0.8 -0.8 35 0.1 1.5 -0.1 -1.5 60 -50 -60 1.3 1.3 45 VBatt- 45 -36 0.9VDD 0.55VDD -31 -27 1.1VDD 0.65VDD 80 100 -30 -30 1.8 -1.8 55 0.5 VDD-0.8 |10| |10| 5 10 4.5 2.0 |10| |10| 6 5.0 0.4 VSCLK = 0Vdc VSCLK = VDD |10| |10| 2.0 VCS = 0Vdc VCS = VDD 30 |10| 100 2.0 VIN5,6 = 0Vdc VIN5,6 = VDD 30 |10| 100 2.0 Conditions Min. Typ. Max. 2.0 Unit V V A A V V A A V V A A V V A A mA mA V V A A A A A A A A A A A A V V V V V
IDRN1-8(Sink) DRN1-8 Current Sink (low side)
ISRC1-6(Sour) SRC1-6 Current Source VSRC1-6=0Vdc, DI=00h, VDRN1-8 =18Vdc (high side) VSRC1-6=0Vdc, DI=00h, VDRN=35V IDRN1-8(Limit) DRN1-8 Current Limit (low side) ISRC1-6(Limit) SRC1-6 Current Limit (high side) VSRC1-6=0Vdc, DI=FFh, VDRN1-8 = 4-16Vdc VSRC1-6=0-12Vdc, DI=FFh, VDRN1-8 = VBatt
VDRN1-8(Cl+) DRN1-8 Clamp Voltage VSRC1-6=0Vdc, DI=00h, IDRN1-8=10mA (low side) VSRC1-6(Cl+)bat SRC1-6 Clamp Voltage VDRN1-8=25V DI=00h, IDRN1-8=10mA (high side) VSRC1-6GND VDRN1-8(Fault) DRN1-8 Fault Voltage (low side) VSRC16(Fault)
VDRN = 10V; ISRC = -10mA VSRC1-6=0Vdc, DI=00h VDRN1-8=VBatt, DI=00h
SRC1-6 Fault Voltage (high side)
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L9848
ELECTRICAL CHARACTERISTCS (continued) DC Characteristics (Tj=-40C to 150C, VDD=4.75Vdc to 5.25Vdc, VBatt=9V to 18V, unless otherwise specified)
Symbol Parameter Tj=110C Tj=25C Tj=-40C 155 5 3.40 0.4 Conditions Min. Typ. 1.5 1.0 Max. 2.0 1.5 1.3 185 15 4.50 0.8 Unit C K V V RDSONDRN1-8 On-Resistance (DRN1-8) TjTS TjTSH PORwih PORwhyst Thermal shutdown junction temperature* Thermal shutdown threshold hysteresis* Power on reset threshold on Power on reset hysteresis
* Guaranteed by design, not tested AC Characteristics (Tj =- 40C to 150C, VDD = 4.75V to 5.25Vdc, VBatt = 9V to 18V, unless otherwise specified)
Symbol Parameter Slew Rate (low side) Turn On Turn Off Delay Time (low side) Turn On Turn Off Delta Slew Rate (high side) Turn On Turn Off Delay Time (high side) Turn On Turn Off Delta Input Capacitance* Output Data (DO) Rise Time Fall Time Access Time Set Up Time Hold Time Disable Time Fault Delay Time (Internal)* Thermal Fault Delay Time (Internal) Conditions See Figures 2 and 3 10 10 See Figures 2 and 3 2 10 20 10 50 20 100 60 s s s 25 25 100 100 s s Min. Typ. Max. Unit
tDRN1-8slewon tDRN1-8slewoff
tDRN1-8delon tDRN1-8deloff tDRN1-8deloffon
tDRN1-8deloff - tDRN1-8delon See Figures 2 and 3
tSRC1-6slewon tSRC1-6slewoff
10 10 See Figures 2 and 3 2 10 20
50 25
100 100
s s
tSRC1-6delon tSRC1-6deloff tSRC1-6deloffon CDI CSCLK tDOrise tDOfall tDOacc tDOset tDOhold tDOdis tFltDlyInt tthFltDlyInt
50
tSRC1-6deloff - tSRC1-6delon
20 100 60 20 20
s s s pF pF ns ns ns ns ns ns s s
50pF from DO to GND, see Fig. 4 50pF from DO to GND, see Fig. 4 50pF from DO to GND, see Fig. 5 50pF from DO to GND, see Fig. 5 50pF from DO to GND, see Fig. 5 No capacitor on DO, see Fig. 1 Duration of open/short fault until Fault Bit is "Set" Duration of thermal fault until Fault Bit is "Set"
30 30 70 20 10 140 100 40 300 50
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L9848
Figure 1. DO loading for disable time measurement
VDD 1 k DO
+5 V 4.0 V tDOdis 1.0 V 0V DO
1 k CS
Figure 2. Output loading for slew rate measurement
Vbatt 600 DRN1-8 3 nF
High Side Configuration
SRC1-6
3 nF
600
Low Side Configuration
Figure 3. Output turn on/off delays and slew rates
IN1-8* IN1-8* OUT1-8
90% 10% 90%
OUT1-8 tDRN1-8slewoff
10%
tDRN1-8slewon tDRN1-8delon
90%
tDRN1-8deloff OUT1-6
90% 10%
OUT1-6
10%
tSRC1-6slewoff tSRC1-6deloff * IN1-4, 7, 8 are available on wafer only.
tSRC1-6slewon tSRC1-6delon
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L9848
Figure 4. SPI input/output slew ratest
tSCLKwid tSCLKlm
90% 10% 90% 10%
tSCLKhm SCLK
tSCLKrise
tSCLKfall
CS tCSrise
90%
tCSfall
10% 90% 10%
DI tDIrise tDOfall
tDIfall
DO tDOrise
Figure 5. SPI timing diagram
CS tCSlead tCSlag
SCLK tDOacc tDOset DO Fault MSB tDIsus tDIhs DI MSB In Bit 14 or 6 Bit 13 or 5 Bits 12 to 0 Bits 6 to 1 Fault LSB DI Data byte tDOhold tDOdis
FUNCTIONAL DESCRIPTION General Features The L9848 IC is a monolithic integrated circuit, which provides high flexibility for driving medium loads. 8 outputs, whereof 6 (Output1-6) can be used as either internal low or high side drives in any combination and 2 are dedicated low side outputs (Output7-8). The use of this device reduces the I/O port requirements of the microprocessor by having serially controlled outputs via a SPI interface. In addition, Output5-6 are capable of being PWMed via an external pin (Input5-6). The 8bit SPI input is used to command the 8 output drivers either ON or OFF and additional to indicate latched fault conditions that may have occurred. Multiple L9848s may be daisychained with one additional microprocessor I/O port (CSn) for each device. The implemented self-configuration allows the user to connect a high or low side load to any of these outputs and the L9848 will drive them correctly
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L9848
as well as provide proper fault mode operation with no other needed inputs. This device switch variable load currents within the operation temperature range. The outputs are MOSFET drivers to minimize Vdd current requirements. There's no VBatt input pin however VBatt is connected to the drains of high side outputs. The L9848 meets all required specifications when the supply voltage applied to the drain(s) of the outputs is within the operating range. For supply voltages applied to the drain(s) down to 6.8V the part is functional however, it does not meet all parametric limits, i.e. output on-state voltages. Outputs - Common Characteristics The 6 self-configuring outputs (Outputs1-6) are able to drive either incandescent lamps, inductive loads (nonPWMed), or resistive loads biased to VBatt. These outputs are enabled and disabled via the SPI bus. Each of these outputs is short circuit current limited and has an over-temperature protection as described under "Functional Description - Thermal Shutdown". When a high side configured output is commanded OFF after having been commanded ON, the source voltage will go to the lesser negative of (VBatt-45V). This is due to the design of the circuitry and the transconductance of the MOSFET. When a low side configured output is commanded OFF after having been commanded ON, the output voltage will rise to the internal zener clamp voltage (40Vdc minimum) due to the flyback of the inductive load. - Output 1-4 These four outputs can be used as either high or low side drives. Integrated current source pull-ups and pull-downs are employed to correctly latch "open load" fault data. Both of these current sources are needed to detect an open load state since these outputs self configure as either high or low side drives. Drain Connections of Output1-4 (DRN1-4) These pins are connected to the drains of the n-channel MOSFET transistors. Source Connections of Output1-4 (SRC1-4) These pins are connected to the sources of the n-channel MOSFET transistors. - Output 5-6 These two self-configuring outputs can be used to drive either high or low side loads. In addition to be controlled by the SPI BUS these outputs can also be enabled and disabled via IN5 and IN6 inputs. IN5 and IN6 inputs are logically ORed with the SPI commands to allow either the IN5-6 inputs or the SPI commands to activate these outputs. The use of IN5-6 for PWM control on these outputs should only be done with non-inductive loads. Integrated current source pull-ups and pull-downs are employed to correctly latch "open load" fault data. Both of these current sources are needed to detect an open since these outputs self configure as either high or low side drives Drain connections of Output5-6 (DRN5-6) These pins are connected to the drains of the n-channel MOSFET transistors. Source connections of Output5-6 (SRC5-6) These pins are connected to the sources of the n-channel MOSFET transistors. - Output7-8 These two outputs (DRN7-8) are dedicated low side drives. Integrated current source pull down are required to correctly latch "open load" fault data. Main Power Input (VDD) The VDD input is the primary power source of the L9848. This supply is used as the power source for all of its
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L9848
logic circuitry and other miscellaneous functions. Notice that if the L9848 is interfaced to a processor operating with a lower voltage (e.g. 3.0 VDC), the microprocessor inputs connected to the L9848 will swing from 0 to 5.0 VDC. Discrete Inputs (IN5-6) These inputs allow Output5-6 to be enabled via this external pin without the use of the SPI. A logic "1" on these inputs enables the corresponding output no matter what the status of the SPI command register. A logic "0" on these inputs disables the corresponding output if the SPI command register is not commanding this output on. These pins can be left "open" if the outputs are controlled only via the SPI (internally pulled down). These inputs are ideally suited for non-inductive loads that are pulse width modulated (PWMed). This allows PWM control without the use of the SPI. The TTL level compatible input voltages allow proper operation with microprocessors that are using 5.0V or 3.0V for their Vdd supply. Serial Peripheral Interface (SPI) A standard serial peripheral interface, consisting of Serial Clock (SCLK), Data Out (DO), Data In (DI), and Chip Select (CS) is implemented to allow access to the internal registers of the L9848. All outputs are controlled via the SPI.The input pins CS, SCLK, and DI have TTL level compatible input voltages allowing proper operation from microprocessors that are using 5.0V or 3.0V for their VDD supply. The design of the L9848 allows a "daisychaining" of multiple L9848's to further reduce the need for controller pins. - Serial Data Output (DO) This output pin is in a tri-state condition when CS is a logic "0" (LOW). When CS is a logic "1" (HIGH), this pin always transmits 8bits of data from the fault register to the digital controller. After the first 8bits data are transmitted the DO output then sequentially transmits the digital data that was just received (8 SCLK cycles earlier) on the DI pin. The DO output continues to transmit the 8 SCLK delayed bit data from the DI input until CS eventually transitions from a logic "1" to a logic "0". DO data changes state 10 ns or later, after the falling edge of SCLK. By definition, the MSB (Table 3) is the first bit of the byte transmitted on DO and the LSB is the last bit of the byte transmitted on DO, once CS transitions from a logic "0" to a logic "1". - Serial Data Input (DI) This input takes data from the digital controller while CS is HIGH. The L9848 accepts an 8bit data stream to command the outputs ON or OFF. By definition, the MSB (Table 1) is the first bit of each byte received on DI and the LSB is the last bit of each byte received on DI, once CS transitions from a logic "0" to a logic "1". - Chip Select (CS) This is the chip select input pin. On the rising edge of CS, the DO pin switches from tri-state to activeout mode. While CS is high, register data is shifted in and shifted out by the DI and DO pin, respectively, on each subsequent SCLK. On the falling edge of CS, the DO pin switches back to tri-state mode and the fault register will be "Cleared" if a valid DI byte was received. A valid DI byte is defined as such: 1st A multiple of 8 bits was received 2nd SCLK was low when CS went low 3rd Current SPI cycle started when SCLK was low The fault data is not cleared unless all of the 3 previous conditions have been met. A SCLK transition must be seen before CS is interpreted as active. To allow sufficient time to reload the fault registers, the CS pin must remain low for a minimum of 1s prior to going high again, before it starts shifting
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L9848
the fault data bits out on the DO pin. CS has an integrated glitch filter for spurious pulses of 50ns or shorter (i.e. no fault data and Outputs1-8 enable status will be altered). For open circuit condition the CS is internally pulled down to GND. - Serial Clock (SCLK) This is the clock signal input for synchronization of serial data transfer. DI data is shifted into the DI input on the rising edge of SCLK and DO data changes on the falling edge of SCLK. SPI DI Input Command Register An input byte (8bits) is routed to the Command Register. The content of this Command Register is given in Table 1 and Table 2. Additional DI data will continue to be wrapped around to the DO pin. If CS will go low before a complete reception of the current byte, this just transmitted byte will be ignored Table 1. Bit Command Register Definition
MSB LSB
OUT8 D07
OUT7 D06
OUT6 D05
OUT5 D04
OUT4 D03
OUT3 D02
OUT2 D01
OUT1 D00
Table 2. Command Register Logic Definition
BIT STATE STATUS
D00-D07 D00-D07
0 1
OUTPUT1-8 are commanded OFF OUTPUT1-8 are commanded ON
Fault Operation The fault diagnostic capability consists of one internal 8bit shift register. Open or shorted load detection is provided by comparing the source or drain voltage with the VDD voltage. When an output connected as either a low side device or a high side device is commanded OFF, an open load can be detected. When an output connected as either a low side device or a high side device is commanded ON a shorted load can be detected. The fault bit is "set" for each channel if a short, open, or over-temperature condition occurs for Outputs1-8. The content of this Fault Register is given in Table 3. The output load status of each individual channel is defined in Table 4. Open and shorts are subsequently re-latched provided they meet the minimum duration criterion and thermal faults will be re-latched provided they meet the duration criterion after CS goes "LOW", if these fault conditions are still present. The fault register is capable of detecting and latching multiple fault conditions (among the 8 outputs) that have occurred between clearing of the fault flags. All of the faults will be cleared on the falling edge of Chip Select (CS). Table 3. Fault Register Definition
MSB LSB
Fault8 D07
Fault7 D06
Fault6 D05
Fault5 D04
Fault4 D03
Fault3 D02
Fault2 D01
Fault1 D00
Table 4. Fault Logic Definition
BIT STATE STATUS
Fault1-8 Fault1-8
0 1
OUT1-8 are not open or shorted (nominal) OUT1-8 are either open or shorted or in thermal shutdown
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L9848
- Initial Fault Register SPI Cycle After initial application of VDD to the L9848, the fault register is "Cleared" by the POR circuitry during the initial SPI cycle, and all subsequent cycles, valid fault data will be clocked out of DO (fault bits). The bits that are "Set" indicate which particular output(s) have a fault condition. - Incandescent Lamp Outputs Software filtering may be needed to ignore fault signals due to the long turn on delay associated with lamp loads. For example, the lamp load channel gets enabled during one SPI cycle. Approximately 20ms-100ms later, a SPI cycle is required to read the correct fault latch data, which will be cleared after the falling edge of CS of that SPI cycle. Configuration for Output1-6 The drain and source pins for each output must be connected in one of the two following configurations (see Figure 6a and Figure 6b). - Low Side Drivers When any combination of Output1-6 are connected in a low side drive configuration the source of the applicable output (SRC1-6) has to be connected to ground. The drain of the applicable output (DRN16) has to be connected to the low side of the load. - High Side Drivers When any combination of Output1-6 are connected in a high side drive configuration the drain of the applicable output (DRN1-6) has to be connected to VBatt. The source of the applicable output (SRC1-6) has to be connected to the high side of the load. DRN1-6 Susceptibility to Negative Voltage Transients For any output(s) connected and used for a high side drive a fast negative transient slew rate does not inadvertently issue a POR (power on reset) or cause parasitic latching to occur. Nevertheless under some conditions it may be necessary to have a ceramic chip capacitor of 10nF to 100nF connected from drain to GND to aid in preventing the occurance of a problem due to very fast negative transient(s) on the drain(s) of the device. Thermal Shutdown Each of the 8 outputs have independent thermal protection circuitry that disables each output driver once the local n-channel MOSFET device temperature reaches the overtemperature shutdown limit. Due to the hysteresis of the enable and disable temperature levels the faulted channel will periodically turn off and on until the fault condition is cleared, the ambient temperature is decreased sufficiently or the output is commanded OFF. Once any individual channel goes into thermal shutdown, a logic "1" is latched into the Fault Register if it meets the thermal fault filter (Note: does NOT go through the open/short fault filter).
Note: Due to the design of the L9848 each output's thermal limit "may not" be truly independent to the extent that if one output is shorted, it may impact the operation of other outputs (due to lateral heating in the die). The user may be required to monitor the fault bits periodically. If a fault bit is "Set" for the last enabled output, and subsequently, fault bits for other enabled outputs start to be "Set", the user will send two SPI write cycles within 100ms of each other. The first SPI write cycle will "Clear" the fault latches. If multiple faults are indicated after the second SPI write cycle, these faults are most likely thermal faults. The user will then disable this output that was most recently enabled. The fault register should be subsequently interrogated to verify proper operations of the other enabled output channels.
Charge Pump Usage The L9848 uses a separate charge pump and oscillator for each of the 6 configurable output channels to provide low RDSON values when connected in a high side configuration These oscillators are operating in a non-synchronous mode of operation. The frequency range of these charge pumps is designed to be above the AM radio
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L9848
band and below 8.0MHz so that harmonics do not get within the FM radio band. Waveshaping Both the turn on and the turn off slew rates on all outputs (OUTPUT1-8) are limited to reduce conducted EMC energy in the vehicle's wiring harness. The characteristic of the turn-on and turn-off voltage is linear, with no discontinuities, during the output driver state transition. POR Register Initialization L9848 wakes up if the VDD supply increases from 0 to 5VDC in 0.3ms to 3ms. The L9848 has a POR circuit, which monitors the VDD voltage. When the VDD voltage reaches roughly 4.1VDC, and remains above this trip level for minimum 20s, the Command and Fault Registers are "cleared". Before VDD reaches this trip level, all eight outputs are guaranteed in OFF-state. After a valid POR has occurred and the VDD voltage falls below the valid high level for a required amount of time, the L9848 is powered down in a fully controlled manner. No outputs will glitch "ON" and no erroneous fault data is allowed on the DO output. Abnormal Voltage Conditions The L9848 survives the following abnormal voltage conditions. - Reverse Battery applied either directly, or through a load to the drain pins (DRN1-6) with the source pins (SRC1-6) connected to a load or to ground (cold lamp, solenoid, etc). - Maximum Negative Transients that force the drains or sources of the outputs going -20V below the module ground. - Ground Offsets with a maximum of -0.5V to 1.0V between the L9848 ground and any load directly connected to a chassis ground in the case of high side loads. If driving a low side load there will not be an offset between the L9848 ground and the load ground. In addition there may be a maximum ground difference between the L9848 ground and any other module interfacing with it of -0.5V to 1.0V or VAC (10200Hz). - Loss of Ground Operation Any outputs are protected to become active in case of lost ground of the L9848 module with the supply is still applied.
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L9848
FUNCTIONAL BLOCK DIAGRAM Figure 6. L9848 with external components
DRN1 SRC1 or DRN1 SRC1
7 6
7 6
5 4
DRN2 SRC2 or DRN2 SRC2
5 4
+5VDC C2 0.01F
VDD
2
22 23
DRN3 SRC3 or DRN3 SRC3
22 23 IN5 IN6 FROM CPU DI CS SCLK DO
20 9 15 16 14 28
24 25
DRN4 SRC4 or DRN4 SRC4 VBATT
24 25
TO CPU
(FAN OUT CAP 50nF)
DRN7
GND
DRN8 1 18 DRN5 100nF 19 SRC5 or DRN5 SRC5 100nF
18 19
11
DRN6 100nF
10
SRC6 or DRN6 SRC6 100nF
11 10
D02AT511
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L9848
APPLICATION EXAMPLES Figure 7. L9848 as mirror axis control motor drivers
Vdd 5V Vbatt
SCK SDI SDO CS SPI + Data Interface Gate Driver Interface
M
Simultaneous motor drive for seat adjustment memory
PWM IN5 PWM IN6
M
GND
Figure 8. L9848 as mirror motor and bulb driver
Vdd 5V Vbatt
LED Chain SCK SDI SDO CS SPI + Data Interface Gate Driver Interface 5W Safety Light Side Turn Indicator
M
PWM IN5 PWM IN6
Sequential motor drive
M
GND
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L9848
Figure 9. L9848 as window lift relay and mirror motor driver
Vdd 5V Vbatt
SCK SDI SDO CS SPI + Data Interface Gate Driver Interface
M
Vbatt
PWM IN5 PWM IN6
M
M
Power window
GND
Figure 10. L9848 as bipolar stepper motor driver
Vdd 5V Vbatt
SCK SDI SDO CS SPI + Data Interface Gate Driver Interface
SM
PWM IN5 PWM IN6
GND
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L9848
Figure 11. L9848 driving approach for 3 bipolar stepper-motors in sequential mode for climate applications as window lift relay and mirror motor driver
Stepper-Motor 1 active
SPI L9848
SM
disabled disabled
1
L9848 disabled disabled
SM
2
SM
3
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L9848
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 0.1 0.35 0.23
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.5 45 (typ.) 18.1 10.65 1.27 16.51 7.6 1.27 0.291 0.016 0.697 0.394 0.004 0.014 0.009 MIN.
inch TYP. MAX. 0.104 0.012 0.019 0.013 0.020
OUTLINE AND MECHANICAL DATA
0.713 0.419 0.050 0.65 0.299 0.050
SO28
8 (max.)
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L9848
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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